1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of generating circuit layouts that are to be formed using self-aligned double patterning (SADP) routing techniques.
2. Description of the Related Art
Photolithography is one of the basic processes used in manufacturing integrated circuit products. At a very high level, photolithography involves: (1) forming a layer of light or radiation-sensitive material, such as photoresist, above a layer of material or a substrate; (2) selectively exposing the radiation-sensitive material to a light generated by a light source (such as a DUV or EUV source) to transfer a pattern defined by a mask or reticle (interchangeable terms as used herein) to the radiation-sensitive material; and (3) developing the exposed layer of radiation-sensitive material to define a patterned mask layer. Various process operations, such as etching or ion implantation processes, may then be performed on the underlying layer of material or substrate through the patterned mask layer.
Of course, the ultimate goal in integrated circuit fabrication is to faithfully reproduce the original circuit design on the integrated circuit product. Historically, the feature sizes and pitches employed in integrated circuit products were such that a desired pattern could be formed using a single patterned photoresist masking layer. However, in recent years, device dimensions and pitches have been reduced to the point where existing photolithography tools, e.g., 193 nm wavelength photolithography tools, cannot form a single patterned mask layer with all of the features of the overall target pattern. Accordingly, device designers have resorted to techniques that involve performing multiple exposures to define a single target pattern in a layer of material. One such technique is generally referred to as multiple patterning, e.g., double patterning. In general, double patterning is an exposure method that involves splitting (i.e., dividing or separating) a dense overall target circuit pattern into two separate, less-dense patterns. The simplified, less-dense patterns are then printed separately on a wafer utilizing two separate masks (where one of the masks is utilized to image one of the less-dense patterns, and the other mask is utilized to image the other less-dense pattern). Further, in some cases, the second pattern is printed in between the lines of the first pattern such that the imaged wafer has, for example, a feature pitch which is half that found on either of the two less-dense masks. This technique effectively lowers the complexity of the photolithography process, improving the achievable resolution and enabling the printing of far smaller features that would otherwise be impossible using existing photolithography tools. The SADP process is one such multiple patterning technique. The SADP process may be an attractive solution for manufacturing next-generation devices, particularly metal routing lines on such next-generation devices, due to better overlay control that is possible when using an SADP process.
As noted above, the integrated circuit design is eventually fabricated by transferring the circuit layout to a semiconductor substrate in a series of layers that collectively will form the features that constitute the devices that make up the components of the integrated circuit. However, before the layout can be fabricated, a validation process of the layout must take place. Layout designers use very sophisticated Electronic Design Automation (EDA) tools and programs when designing circuit layouts for modern integrated circuit products. As it relates to double patterning techniques, an overall target pattern must be what is referred to as double-patterning-compliant. In general, this means that an overall target pattern is capable of being decomposed into two separate patterns that each may be printed in a single layer using existing photolithography tools. Layout designers sometimes speak of such patterns with reference to “colors,” wherein the first mask will be represented in the EDA tool using a first color and the second mask will be represented in the EDA tool using a second, different color. To the extent a layout is non-double-patterning-compliant, it is sometimes stated to present a “coloring conflict” between the two masks. An overall target pattern may have many regions or areas that cannot be printed because the features in those regions are spaced too closely to one another for existing photolithography tools to be able to print such closely spaced features as individual features. To the extent an overall target pattern has an even number of such features, such a pattern is sometimes referred to as an “even cycle” pattern, while an overall target pattern that has an odd number of such features is sometimes referred to as an “odd cycle” pattern. Even cycle patterns can be formed using double patterning techniques, while odd cycle patterns cannot be formed using double patterning techniques.
FIGS. 1A-1K depict one illustrative example of a device 10 wherein an illustrative prior art SADP process was performed to form metal features, e.g., metal lines, in a layer of insulating material 12. With reference to FIG. 1A, a hard mask layer 14 is formed above the layer of insulating material 12 and a layer of mandrel material 16 was formed above the hard mask layer 14. Also depicted is a patterned layer of photoresist material 17, typically referred to as a “mandrel mask,” that was formed above the layer of mandrel material 16 using traditional, single exposure photolithography tools and techniques. The layer of mandrel material 16 may be comprised of a material that may be selectively etched with respect to the hard mask layer 14.
Next, as shown in FIG. 1B, an etching process is performed on the layer of mandrel material 16 while using the patterned layer of photoresist material 17 as an etch mask. This etching process results in the formation of a plurality of mandrels 16A. In the depicted example, the mandrels 16A are formed so as to have a pitch 16P and a minimum width 16W. The pitch 16P and the width 16W may vary depending upon the particular device 10 under construction. FIG. 1C depicts the device 10 after the patterned layer of photoresist 17, i.e., the mandrel mask, has been removed.
Next, as shown in FIG. 1D, a layer of spacer material 18 was deposited on and around the mandrels 16A by performing a conformal deposition process. The layer of spacer material 18 should be a material that may be selectively etched relative to the mandrels 16A and the hard mask layer 14. FIG. 1E depicts the device 10 after an anisotropic etching process was performed on the layer of spacer material 18 to define a plurality of sidewall spacers 18A, having a lateral width 18W, positioned adjacent the mandrels 16A. The width 18W of the spacers 18A may vary depending upon the particular device 10 under construction. Next, as shown in FIG. 1F, the mandrels 16A are removed by performing an etching process that is selective relative to the hard mask layer 14 and the sidewall spacers 18A.
FIG. 1G depicts the device 10 after a patterned photoresist mask 20, a so-called block mask, is formed above the layer of spacers 18A and the hard mask layer 14. In one example, the block mask 20 may be formed using traditional, single exposure photolithography tools and techniques. FIG. 1H depicts the device 10 after an etching process has been performed to transfer the pattern defined by the combination (or union) of the sidewall spacers 18A and the block mask 20 to the hard mask layer 14. FIG. 1I depicts the device 10 after one or more process operations were performed to remove the sidewall spacers 18A and the block mask 20 from above the now-patterned hard mask layer 14. Next, as shown in FIG. 1J, an etching process was performed on the layer of insulating material 12 through the patterned hard mask 14 to define illustrative trenches 22 in the layer of insulating material 12. FIG. 1K depicts the device 10 after schematically depicted metal features 24, e.g., metal lines, were formed in the trenches 22 and after the patterned hard mask layer 14 was removed. The manner in which such metal features 24 may be formed in the layer of insulating material 12 are well known to those skilled in the art.
In the SADP process, the metal features 24 that are formed are typically referred to as either “mandrel-metal” features (“MM”) or “non-mandrel-metal” features (“NMM”). As depicted in FIG. 1K, the metal features 24 that are positioned under the location where the mandrels 16A and the features of the mandrel mask 17 (both shown in dashed lines in FIG. 1K) were located, are so-called “mandrel-metal” features—designated as “MM” in FIG. 1K. All of the other metal features 24 formed in the layer of insulating material 12 are “non-mandrel-metal” features—designated as “NMM” in FIG. 1K. As it relates to terminology, the MM features and NMM features are referred to as being different “colors” when it comes to decomposing an overall pattern layout that is intended to be manufactured using an SADP process, as will be described more fully below. Thus, two MM features are said to be of the “same color” and two NMM features are said to be of the “same color, while an MM feature and an NMM feature are said to be of “different colors.”
Another important feature that is employed in SADP techniques is a so-called “dummy mandrel.” FIGS. 1L-1M each include a sequence of drawings (top to bottom) that will be referenced to explain the concept of a dummy mandrel. The upper drawing in FIG. 1L depicts the device 10 after the original mandrels 16A and the spacers 18A have been formed as previously described. As discussed previously, mandrel-metal (MM) features are only formed below spaces previously occupied by a mandrel 16A.
In the cross-sectional view shown in FIG. 1L, mandrel 16A is a mandrel that occupies a space where a mandrel-metal (MM) feature 24 will be formed (see lower drawing) in the layer of insulating material 12, while the two other depicted mandrels 16AD are “dummy mandrels”—where there will be no mandrel-metal formed thereunder. Also depicted in the lower drawing in FIG. 1L is a non-mandrel-metal (NMM) feature 24 that is formed in the space defined by two adjacent spacers 18A. At the point in the process flow depicted in the middle drawing in FIG. 1L, all of the original mandrels 16A have been removed, leaving only the spaced-apart spacers 18A, and a block mask 20 has been formed that covers the area previously occupied by portions of the original mandrels 16A, thereby effectively converting portions of the original mandrels 16A that are now covered by the block mask 20 into “dummy mandrels” 16AD, which are shown in dashed lines in the middle drawing for explanation purposes. As will be understood from the foregoing, a dummy mandrel, e.g., mandrels 16AD in FIG. 1L, is a portion of an original mandrel 16A whose position is later covered by the block mask 20 after the original mandrel 16A has been removed. In the lower drawing in FIG. 1L dashed lines 24D depict the location where a mandrel-metal (MM) feature would have been formed if the block mask 20 did not block the areas previously occupied by the dummy mandrels 16AD.
FIG. 1M is a sequence of plan-view drawings schematically depicting some of the steps involved in forming two illustrative mandrel-metal features 24 (see bottom drawing) in the layer of insulating material 12. As depicted, the original mandrels 16A are typically line-type features that may be of any desired axial length. In some cases, the original mandrels 16A may be formed so as to exhibit a “jogged-line” configuration. In general, as discussed above, a “dummy mandrel” is a portion of the original mandrel 16A that is later covered by the block mask 20 after the original mandrel 16A has been removed. The upper drawing in FIG. 1M depicts the point in the process flow wherein the spacers 18A have been formed adjacent an illustrative original mandrel 16A. The next drawing in the sequence depicts the point in the process flow where the original mandrel 16A has been removed. The hard mask layer 14 is not depicted in FIG. 1M. The next drawing depicts the point in the process flow where the block mask 20 has been formed so as to cover a portion, but not all, of the space previously occupied by the original mandrel 16A. The bottom drawing depicts the device after the layer of insulating material 12 has been etched, the block mask 20 and spacers 18A have been removed, the mandrel-metal (MM) features 24 have been formed in the layer of insulating material 12 and after the hard mask 14 (not shown) has been removed. In this example, with reference to the upper drawing in FIG. 1M, the middle portion of the original mandrel 16A would be referred to as a “dummy mandrel,” while the remaining portions of the original mandrel 16A are still referred to as “mandrels.” That is, the block mask 20 is used to effectively “cut” what would otherwise become part of a mandrel-metal feature 24. The dummy mandrel patterns are traditionally generated by SADP decomposition software.
One well-known double patterning technique is referred to as LELE (“litho-etch-litho-etch) double patterning. As the name implies, the LELE process involves forming two photoresist etch masks and performing two etching processes to transfer the desired overall pattern to a hard mask layer that is then used as an etch mask to etch an underlying layer of material. With respect to terminology, the different masks employed in the LELE double patterning process are said to be different “colors.” Thus, depending upon the spacing between adjacent features, the features may be formed using the same photoresist mask (“same color”) or they may have to be formed using different photoresist masks (“different color”). In an LELE process, if two adjacent features are spaced apart by a distance that can be patterned using traditional single exposure photolithography, then those two adjacent features may be formed using the same (“same color”) photoresist mask. In contrast, if the spacing between the two adjacent features is less than can be formed using single exposure photolithography, then those features must be either formed using different photoresist masks (“different color”) or the spacing between the features must be increased by changing the circuit layout such that they may be formed using the same photoresist mask.
As noted above, any circuit layout to be formed using double patterning techniques must be checked to confirm that it can be decomposed into two separate photoresist masks. A layout must have zero odd-cycles to be decomposable in an LELE process. To determine if a circuit layout is double-patterning-compliant, a mask engineer, using very sophisticated and well-known EAD tools and computer programs, connects adjacent features by “drawing” a “polygon loop” that connects the centroid of the features under investigation. FIG. 1N contains a simplistic example of such a polygon loop 30 drawn for five (A-E) adjacent features. The polygon loop 30 is comprised of five edges 31. In this example, due to the relative spacing between adjacent features, all of the features are required to be formed using “different color” (“DC”) masks. Thus, the polygon loop 30 has five “DC” edges connecting the various features. The polygon loop 30 represents an odd-cycle layout due to the odd number of DC edges (five total) in the polygon loop 30. Due to the odd number of DC edges in the polygon loop 30, the pattern reflected by the polygon loop 30 is not decomposable using double patterning techniques. FIG. 1O depicts one illustrative modification that may be made to the circuit layout to make it decomposable. In this example, the spacing between the features A and B is increased such that those two features may be formed using the “same color” (SC) mask. Thus, the modified polygon loop 30A now has only four DC edges—an even number—and it may be decomposed using double patterning techniques. In short, in the LELE double patterning process, increasing the spacing between the adjacent features has the effect of “breaking” the odd-cycle polygon loop. However, increasing the spacing between adjacent features has the negative effect of increasing the area or “plot space” of silicon needed to fabricate the circuit, and increasing such spacing may have a “ripple” effect, causing additional odd-cycles that will need to be resolved.
In the SADP process, just like with the LELE process, a layout must have zero odd-cycles to be decomposable. However, unlike the LELE process, due to the nature of the SADP process, merely increasing the spacing between adjacent features within an odd-cycle polygon loop such that the two adjacent features must be formed using the “same color” mask will not resolve an odd-cycle situation, i.e., such an increase in spacing will not break the odd-cycle loop in the SADP process. Rather, in the SADP process, the spacing between the two adjacent features must be increased by a sufficient magnitude such that the two adjacent features are spaced so far apart that they may be formed using either the mandrel mask or the block mask—i.e., the spacing must be increased to such an extent that the features are said to be “color insensitive.” As before, increasing the spacing between adjacent features has the negative effect of increasing the area or “plot space” of silicon needed to fabricate the circuit, and increasing such spacing may have a “ripple” effect, causing additional odd-cycles that will need to be resolved by increasing the spacing between additional features.
As noted above, the integrated circuit design is eventually fabricated by transferring the circuit layout to a semiconductor substrate in a series of layers that collectively will form the features that constitute the devices that make up the components of the integrated circuit. However, before the layout can be fabricated, a validation process of the layout must take place. Design Rule Checking (DRC) is the area of electronic design automation that determines whether the physical layout of a particular chip layout satisfies a series of recommended parameters called design rules. Design rule checking is a major step during physical verification of the chip design. Design rules are a series of parameters provided by semiconductor manufacturers that enable the chip designer to verify the correctness of a product layout and the mask sets (reticle) used in manufacturing the product. Advanced processes and products may involve the use of more restrictive design rules in an effort to improve product yield.
Design rules may be specific to a particular semiconductor manufacturing process and/or product. In general, a design rule set specifies certain geometric and connectivity restrictions between features of the layout to ensure sufficient margins to account for variability in semiconductor manufacturing processes and to ensure that the circuits work as intended. Typically, there are several basic types of design rules that semiconductor manufacturers employ. The first are single layer rules, such as, for example, width rules, spacing rules and pitch rules. A width rule specifies the smallest allowable width of any shape in the design, i.e., the width of a metal line or a gate electrode structure. A spacing rule specifies the minimum distance between two adjacent features, like the spacing between two adjacent metal lines. Spacing rules can vary depending upon the nature of the relationship between the two adjacent features, e.g., corner-to-corner spacing, tip-to-side spacing, side-to-side spacing, tip-to-tip spacing, etc. The magnitude of the space allowed by these various spacing rules will likely not be the same in all situations, e.g., the allowable tip-to-tip spacing may be different from the allowable side-to-side spacing. Additionally, the magnitude of the allowed spacing will likely be tighter (smaller) for more advanced products and processes as compared to older product generations. These single layer rules will exist for each layer of a semiconductor product, with the lowest levels typically having the tightest or most restrictive design rules and the highest metal layers on the product typically having larger, less restrictive design rules. There is also what is known as two layer design rules. A two layer design rule specifies a relationship that must exist between features on two separate layers of the product. For example, an enclosure design rule might specify that an object of one type, such as a contact or via, must be covered, with some additional margin of error, by a metal layer. There are many other design rules that are not discussed herein.
Typically, the design validation process is handled by a computer-based verification tool, which processes a circuit layout and verifies that the layout adheres to a set of specified design rules. One such verification tool is sometimes referred to as a design rule checker. Often times the design rule checker is implemented as a stand-alone software program, such as Cadence Assura®DRC, or as a part of an electronic design automation tool, such as Cadence Virtuoso®. The design rule checker examines a layout for violations of a set of specified design rules. The layout is usually received by the design rule checker in the form of a file that digitally represents the layout of the circuit. Current formats for layout files include, but are not limited to, GDS II and OASIS. When a design rule checker observes a circuit feature within the layout that violates a particular design rule, the violation is flagged by the design rule checker. Examples of how this flagged violation can be brought to the designer's attention include, but are not limited to, marking the violation directly in a resulting output layout file or graphically bringing attention to the violation within the electronic design automation tool.
Design rule checking and double patterning checking are very computationally intense tasks. Usually, design rule checks will be run on each sub-section of a product to minimize the number of errors that are detected at the top level. If run on a single CPU, customers may have to wait up to a week to get the result of a design rule check for modern integrated circuit designs. Most design companies need to or would like to reduce the time involved in performing design rule checking/double patterning checking operations, i.e., it is desirable to achieve reasonable cycle times since design rule checking/double patterning checking operations will likely be performed several times prior to producing a final circuit layout that is both design-rule and double-patterning-compliant. With today's processing power, full-chip design rule checking/double patterning checking operations may be performed more quickly. Nevertheless, reducing the time involved in validating and correcting errors in a product layer such that the final product layout is design-rule-compliant and double-patterning-compliant is a highly desirable goal.
FIG. 2 depicts one illustrative example of a prior art metal routing process 50 that is performed using EDA tools for generating a circuit routing layout 58 that is intended to be manufactured using an SADP process. As shown in FIG. 2, the process begins with creating a set of mandrel mask rules, as indicated in block 52, and creating a set of block mask rules, as indicated in block 56. The mandrel mask rules and the block mask rules may be specific to a particular semiconductor manufacturing process and/or product. In general, mandrel mask rules and the block mask rules establish, among other things, certain size and spacing limitations as it relates to the formation of features on both the mandrel mask and the block mask, while accounting for the limitations in photolithography tools and techniques. With continuing reference to FIG. 2, based upon the mandrel mask rules and the block mask rules, a set of metal routing design rules are generated, as indicated in block 56. In general, the metal routing design rules set specifies certain geometric and spacing restrictions between adjacent features of the circuit layout, while accounting for variability in semiconductor manufacturing processes. Importantly, the metal routing design rules are generated and used to create the final circuit layout in an effort to insure that the final circuit layout can be decomposed into a mandrel mask and a block mask, each or which is compliant with the corresponding mask rules. With the metal routing rules established (in block 56), an EDA router is used to generate the circuit routing layout 58.
An ideal method of implementing a double patterning route would be a colorless routing method, wherein EDA Route software generates a metal layout without assigning color to metal route patterns and the decomposability of route layout is assured by enforcing zero odd cycle. The colorless route method is preferred over otherwise color route method because it does not require color assignment (decomposition) during routing process and is thus much more efficient. The colorless route method requires that the layout must have color symmetry. FIG. 3 depicts an example of such a color-symmetrical layout as it relates to an LELE double patterning process. The overall circuit layout consists of three features (A-C). In one coloring possibility (“Color Assignment 1”), the feature B is formed in mask A, while the features A and C are formed in mask B. In another coloring possibility (“Color Assignment 2”), the color assignment is flipped or reversed from Color Assignment 1, where the features A and C are formed in mask A, while the feature B is formed in mask B. The circuit design layout is said to be color symmetrical if both of the colored layouts in FIG. 3 have passed all required design rule checking or if both of the colored layouts fail the exact same design rule check. Color symmetry is naturally guaranteed for the LELE double patterning process where mask A and mask B are symmetrical.
However, due to the nature of the SADP process, such color symmetry is not guaranteed due to the nonsymmetrical design rules between mandrel-metal (MM) features and non-mandrel-metal (NMM) features. The non-color-symmetry of an SADP layout can also originate from prior art SADP decomposition solutions. FIG. 4A depicts an example of the non-color-symmetrical nature of the SADP process. In one SADP coloring possibility (“Color Assignment 1”), the feature B is a mandrel-metal (MM) feature, while the features A and C are non-mandrel-metal (NMM) features. In another SADP coloring possibility (“Color Assignment 2”), the features A and C are MM features, while the feature B is an NMM feature. Assuming that the spacing “S” (shown in the bottom drawing in FIG. 4A) between the mandrel-metal features A and C in the Color Assignment 2 solution is less than the minimum mandrel spacing rules, then the Color Assignment 2 solution is not DRC compliant. However, with respect to the Color Assignment 1 solution, the features A and C are non-mandrel-metal features and not subject to design rule checking of the minimum mandrel spacing rules, thus the Color Assignment 1 solution is DRC compliant, which is opposite to the Color Assignment 2. Therefore, the design layout herein is not color symmetrical according to prior art SADP design rules.
FIG. 4B depicts another example of the non-color-symmetrical nature of the SADP process that originates from decomposition solution. In one SADP coloring possibility (“Color Assignment 1”), the features A, C and E are NMM features, while the features B, D and F are MM features. To resolve mandrel patterning in the Color Assignment 1 routing, dummy mandrels (collectively referenced with the number 70) are formed to connect the closely spaced mandrel metals. The outline of the block mask 20 that will be used to prevent metal formation in the dummy mandrel region is depicted in dashed lines in FIG. 4B.
In another SADP coloring possibility (“Color Assignment 2”), the features A, C and E are MM features, while the features B, D and F are NMM features. To resolve mandrel patterning in the Color Assignment 2 routing, dummy mandrels (collectively referenced with the number 72) are formed to connect the closely separated mandrel metals. A block mask 20 is still in use to prevent metal formation in the dummy mandrel region. As depicted, the configurations of the areas occupied by the dummy mandrels 70, 72 that are formed to resolve the design layout are not the same.
With continuing reference to FIG. 4B, the block mask 20 is depicted as having an ideal rectangular configuration. However, when actually manufactured, the block mask 20 will typically not have this idealized rectangular configuration. For example, FIG. 4B also includes a dashed line that depicts an example of the configuration of an as-manufactured real-world block mask 20R that has rounded corners as compared to the theoretical configuration of the rectangular shaped block mask 20. The general oval-shaped configuration of the real-world block mask 20R is also individually depicted in FIG. 4B for clarity purposes. Accordingly, due to differences between the theoretical and real-world configuration of the block mask and the fact that the features A-F will also suffer some “distortion” as compared to the idealized shape of those features, the Color Assignment 1 routing depicted in FIG. 4B may not pass design rule checks. For example, due to the “corner rounding” in both block mask 20 and mandrel feature F, there is unanticipated metal feature formed in the dummy mandrel region that will result in a violation of the spacing requirement between the features E and F. On the other hand, the design layout under Color Assignment 2 can be manufactured with the decomposition result shown. More importantly, the SADP design layout herein is not color symmetrical because of the non-symmetrical decomposition solutions, more specifically, dummy mandrel formation.
Thus, using prior art SADP techniques, the formation of colorless circuits using colorless SADP routing method was not possible. This is problematic for several reasons. First, colored routing solutions require very time-consuming decomposition-coloring conflict resolution processes. Additionally, coloring-dependent decomposition of circuit layouts typically results in unintended coloring-dependent performance variations in the resulting integrated circuit product.
The present disclosure is directed to various methods of generating circuit layouts that are to be formed using self-aligned double patterning (SADP) routing techniques which may solve or at least reduce one or more of the problems identified above.